Module 16: I/O Organization & Interrupt Handling

Tags: #◇Computer Science #◇CSARCH2 #◇Computer Architecture #◇Hardware Modeling #◇I/O Organization & Interrupt Handling

◇Overview

Modern microprocessors interact with an extensive variety of peripheral devices—solid-state storage controllers, network interface cards (NICs), graphics processing units (GPUs), and human input interfaces—that operate at vastly disparate data rates and clock domains. This module examines the architectural organization of the Input/Output subsystem. We contrast Memory-Mapped I/O vs. Port-Mapped (Isolated) I/O, evaluate the three fundamental I/O transfer paradigms (Programmed I/O, Interrupt-Driven I/O, and Direct Memory Access), analyze hardware bus arbitration schemes, and formalize the exact microarchitectural lifecycle of hardware interrupt dispatching.

◇Key Definitions

• I/O Module / Interface: The hardware controller bridging the system bus and a peripheral device, handling data buffering, voltage level translation, status reporting, and command decoding.
• Memory-Mapped I/O (MMIO): An addressing scheme where peripheral device control, status, and data registers share the exact same physical address space as main memory, allowing standard load/store instructions (MOV, LDR, STR) to interact with hardware.
• Port-Mapped / Isolated I/O (PMIO): An addressing scheme where peripheral devices reside in a physically isolated I/O address space, accessed exclusively via dedicated machine instructions (e.g., x86 IN and OUT) and distinguished by an $M/\overline{IO}$ bus signal.
• Programmed I/O (Polling): A data transfer technique where the CPU continuously checks a peripheral's status register in a synchronous busy-wait loop until the device is ready.
• Interrupt-Driven I/O: An asynchronous data transfer technique where the peripheral signals its readiness by asserting an electrical interrupt line (INTR), freeing the CPU to execute other tasks until serviced.
• Direct Memory Access (DMA): A high-performance hardware transfer mechanism where a dedicated DMA Controller (DMAC) takes mastership of the system bus to transfer blocks of data directly between I/O devices and main memory without routing bytes through CPU registers.
• Interrupt Vector Table (IVT): An array of function pointers stored in memory mapping interrupt vector numbers to their corresponding Interrupt Service Routine (ISR) entry points.

◇Theoretical Framework / Core Concepts

1. Memory-Mapped I/O vs. Port-Mapped I/O

Memory-Mapped I/O (ARM, RISC-V, PCIe):
+-------------------------------------------------------------------------+
| [ Physical RAM Space (0x00000000 - 0xEFFFFFFF) ]                        |
+-------------------------------------------------------------------------+
| [ I/O Device Registers / PCIe BARs (0xF0000000 - 0xFFFFFFFF) ]          |
+-------------------------------------------------------------------------+
- Uses standard CPU instructions: MOV [0xF0001000], EAX

Port-Mapped / Isolated I/O (x86 Legacy Ports):
+------------------------------------+  +--------------------------------+
| Physical RAM Space (Memory Bus)   |  | Isolated I/O Ports (0x0000-FFFF|
| (Accessed via standard MOV/LOAD)   |  | (Accessed via IN / OUT instrs) |
+------------------------------------+  +--------------------------------+
- Dedicated M/~IO bus control line distinguishes memory vs. I/O transactions.

2. The Three Fundamental I/O Data Transfer Paradigms

3. Direct Memory Access (DMA) Mechanics & Transfer Modes

The DMA Controller (DMAC) sits directly on the system bus alongside the CPU:

DMA Operational Transfer Modes:

1. Burst Mode (Block Transfer):
   • The DMAC requests the bus ($HRQ$), receives mastership ($HLDA$), and transfers the entire data block (e.g., 64 KiB) without interruption.
   • Trade-off: Maximizes transfer throughput, but locks the CPU out of memory for the duration of the burst.
2. Cycle Stealing Mode:
   • The DMAC requests the bus for a single bus cycle, transfers one word, and immediately relinquishes the bus back to the CPU.
   • Trade-off: Interleaves I/O data transfers with CPU instruction execution, minimizing processor stalling.
3. Transparent Mode:
   • The DMAC transfers data only during clock cycles when it detects that the CPU is executing internal operations (e.g., ALU multiply) without utilizing the external system bus.

4. Hardware Interrupt Processing Lifecycle

When an external hardware device requests CPU service:

1. Device asserts INTR line on processor pin.
2. CPU finishes executing the CURRENT machine instruction.
3. CPU samples INTR; if interrupts are enabled (IF=1):
   - CPU emits INTA (Interrupt Acknowledge) signal on control bus.
   - Device places its 8-bit Interrupt Vector Number onto data bus.
4. Hardware Context Save:
   - CPU pushes FLAGS register, Code Segment (CS), and Return EIP/RIP onto the Stack.
5. CPU multiplies Vector Number by 4 (or 8) to index the Interrupt Vector Table.
6. CPU loads the target Interrupt Service Routine (ISR) address into PC/EIP.
7. CPU executes ISR code.
8. ISR ends with IRET (Interrupt Return) instruction:
   - CPU pops saved context (FLAGS, EIP) off the stack.
   - Normal program execution resumes seamlessly.

◇Worked Examples / Calculations / Hardware Traces

Example 1: CPU Utilization Analysis (Polling vs. Interrupts vs. DMA)

Problem: A high-speed network controller receives data at a continuous rate of $10\text{ MB/s}$ in $1\text{ KiB}$ packets ($1024\text{ bytes}$). The CPU runs at a clock frequency of $2.0\text{ GHz}$.

• Polling: Checking the device status register takes 50 clock cycles. The CPU must poll at twice the packet arrival rate to prevent buffer overflow.
• Interrupts: Each 1-byte read in an ISR requires an interrupt handling overhead of 400 clock cycles.
• DMA: The DMAC transfers each 1 KiB packet in cycle-stealing mode. Initializing the DMAC takes 100 clock cycles, and servicing the final completion interrupt takes 300 clock cycles.

Calculate the percentage of total CPU capacity consumed under each paradigm.

Solution:

• Packet Arrival Rate:
  $\text{Packets per second} = \frac{10 \times 10^6\text{ B/s}}{1024\text{ B/packet}} \approx 9,765.625\text{ packets/s}$
• Total CPU Cycles per second: $2.0 \times 10^9\text{ cycles/s}$.

1. Programmed I/O (Polling):

   • Polling frequency $= 2 \times 9,765.625 = 19,531.25\text{ polls/s}$.
   • If dedicated polling loop is running continuously: $100\%$ CPU Utilization (Core is locked in while loop).

2. Interrupt-Driven I/O (Byte-by-Byte Interrupts):

   • Interrupts per second $= 10\text{ million bytes/s} = 10^7\text{ interrupts/s}$.
   • CPU cycles required $= 10^7 \times 400\text{ cycles} = 4.0 \times 10^9\text{ cycles/s}$.
     $\text{CPU Utilization} = \frac{4.0 \times 10^9}{2.0 \times 10^9} \times 100\% = 200\% \implies \mathbf{System\ Crashes\ (Buffer\ Overflow)}$

3. Direct Memory Access (DMA):

   • Total overhead per 1 KiB packet $= 100\text{ cycles (setup)} + 300\text{ cycles (ISR)} = 400\text{ cycles per packet}$.
   • Cycles per second $= 9,765.625 \times 400\text{ cycles} = 3,906,250\text{ cycles/s}$.
     $\text{CPU Utilization} = \frac{3,906,250}{2.0 \times 10^9} \times 100\% \approx 0.195\%$

Conclusion: DMA reduces CPU overhead from a system-halting $200\%$ down to less than $0.2\%$, enabling multi-gigabit network throughput.

◇Complexity Analysis / Common Pitfalls

• Neglecting to Preserve Registers in ISRs: A critical systems programming error is failing to save and restore general-purpose registers modified inside an Interrupt Service Routine. Because interrupts arrive asynchronously, modifying EAX without pushing/popping it corrupts the interrupted user process.
• Cache Incoherence with DMA: When a DMA controller writes data directly into physical DRAM, the CPU's cache may still contain stale copies of those memory lines. Systems must employ hardware cache snooping (Bus Snooping) or explicit software cache invalidation instructions before reading DMA buffers.
• Interrupt Storms / Priority Inversion: Unmasking high-frequency hardware interrupts without rate limiting can cause an "Interrupt Storm" where the CPU spends $100\%$ of its time entering and exiting ISRs, starving background application threads.

◇References & Navigation

• Previous Topic: ◇Virtual Memory & Address Translation (Paging & TLB)
• Next Topic: ◇Pipelining Fundamentals & Pipeline Hazards
• Related Notes: ◇Processing Unit Organization & Single-Bus Datapath, ◇Functional Units & Performance Fundamentals